PhD student @ HKBUI am Wenjun Yu (俞文军), a second-year Ph.D. student in Computer Science at Hong Kong Baptist University, supervised by Prof. Amelie Chi Zhou. Prior to that, I received my B.S. in Artificial Intelligence from Dalian University of Technology.
My research interests lie broadly in DLRM training/serving optimization, generative RecSys acceleration and GPU Virtualization techniques.
Outside of my academic work, I'm deeply curious about traditional Chinese metaphysics. I've explored systems such as Bazi, Ziwei Doushu, and Xiao Liu Ren, and enjoy studying how these classical frameworks interpret patterns, fate, and decision-making. Explore my life Bazi score K-line chart here.
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Wenjun Yu, Amelie Chi Zhou, Shuguang Han — Alibaba (XianYu)
(SC 2026, CCF-A (19.2%)) International Conference for High Performance Computing, Networking, Storage, and Analysis
Generative Recommender inference faces a dual memory bottleneck absent in LLM serving: embedding hot caches and KV caches compete for the same limited GPU HBM, yet existing systems optimize them in isolation. We present RACER, which jointly reallocates HBM between the two caches at runtime and routes requests via a joint EMB–KV-aware scheduler, reducing P99 latency by 24–38% while maintaining ≥93.5% SLO satisfaction across production workload regimes.
Wenjun Yu, Amelie Chi Zhou, Shuguang Han — Alibaba (XianYu)
(SC 2026, CCF-A (19.2%)) International Conference for High Performance Computing, Networking, Storage, and Analysis
Generative Recommender inference faces a dual memory bottleneck absent in LLM serving: embedding hot caches and KV caches compete for the same limited GPU HBM, yet existing systems optimize them in isolation. We present RACER, which jointly reallocates HBM between the two caches at runtime and routes requests via a joint EMB–KV-aware scheduler, reducing P99 latency by 24–38% while maintaining ≥93.5% SLO satisfaction across production workload regimes.

Wenjun Yu, Sitian Chen, Amelie Chi Zhou, Cheng Chen— ByteDance (Douyin)
(HPCA 2026, CCF-A (19.7%)) IEEE International Symposium on High-Performance Computer Architecture
Updating online DLRMs is challenging due to their large model size. We address this by leveraging idle online CPU resources to perform continuous updates, thereby maintaining model freshness. Our approach employs dynamic rank adaptation and NUMA-aware resource scheduling to deliver these updates, significantly improving recommendation accuracy without impacting inference latency.
Wenjun Yu, Sitian Chen, Amelie Chi Zhou, Cheng Chen— ByteDance (Douyin)
(HPCA 2026, CCF-A (19.7%)) IEEE International Symposium on High-Performance Computer Architecture
Updating online DLRMs is challenging due to their large model size. We address this by leveraging idle online CPU resources to perform continuous updates, thereby maintaining model freshness. Our approach employs dynamic rank adaptation and NUMA-aware resource scheduling to deliver these updates, significantly improving recommendation accuracy without impacting inference latency.